Generating RTL Synthesizable Code from Behavioral Testbenches for Hardware-Accelerated Verification
- Resource Type
- Conference
- Authors
- Kakoee, Mohammad Reza; Riazati, Mohammad; Mohammadi, Siamak
- Source
- 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools Digital System Design Architectures, Methods and Tools, 2008. DSD '08. 11th EUROMICRO Conference on. :714-720 Sep, 2008
- Subject
- Computing and Processing
Hardware design languages
Circuit testing
Life estimation
Circuit simulation
System testing
Emulation
Software performance
Design methodology
Design engineering
Writing
- Language
Hardware Accelerated Simulation is widely used in validation of complicated hardware designs. The process of designing a circuit consists of writing the HDL code, and writing and applying the testbenches to the design. Unfortunately, testbenches are often not synthesizable and cannot be used in hardware accelerated simulation. In this paper we propose a method to convert an existing non-synthesizable testbench to a synthesizable one, and apply it to some case studies to show its effectiveness in the hardware accelerated simulation.