Area optimization in 8T SRAM cell for low power consumption
- Resource Type
- Conference
- Authors
- Sarker, M.S.Z.; Hossain, M.; Hossain, N.; Rasheduzzaman, M.; Islam, M.A.
- Source
- 2015 International Conference on Electrical & Electronic Engineering (ICEEE) Electrical & Electronic Engineering (ICEEE), 2015 International Conference on. :117-120 Nov, 2015
- Subject
- Communication, Networking and Broadcast Technologies
Engineered Materials, Dielectrics and Plasmas
Photonics and Electrooptics
Power, Energy and Industry Applications
SRAM cells
Power demand
Transistors
MOS devices
CMOS integrated circuits
Cache memory
CMOS logic
SRAM
VLSI
Power Consumption
- Language
Cache memory plays an important role in high speed electronic devices. SRAM is the key element of cache memory. Cache memory is used for their high speed and SRAM is the element which provides speed to the cache. So this work is mainly concentrated on the simulation and analysis of 8T SRAM cells and their comparative analysis of different parameters such as width to length ratio, capacitance and power consumption. All the simulation has been carried out using Microwind and DSCH2 EDA tool.