Novel Architecture for Lifting Discrete Wavelet Packet Transform With Arbitrary Tree Structure
- Resource Type
- Periodical
- Authors
- Singh, G.; Chiluveru, S.R.; Raman, B.; Tripathy, M.; Kaushik, B.K.
- Source
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems IEEE Trans. VLSI Syst. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on. 29(7):1490-1494 Jul, 2021
- Subject
- Components, Circuits, Devices and Systems
Computing and Processing
Computer architecture
Wavelet packets
Discrete wavelet transforms
Registers
Very large scale integration
Hardware
Complexity theory
Arbitrary tree structure
bit-reordering
discrete wavelet packet transform (DWPT)
signal flow graph (SFG)
- Language
- ISSN
- 1063-8210
1557-9999
This brief presents a novel pipelined VLSI architecture for computing discrete wavelet packet transform (DWPT) with an arbitrary wavelet tree. Coefficients for different levels are computed in a series of stages. Each stage consists of a bypassed wavelet filter and circuit for reordering intermediate coefficients. The proposed lifting-based wavelet filter computes high- and low-pass coefficients in series. In order to accommodate the arbitrary tree structure, the filter either computes the coefficients or bypass the samples. The reordering of intermediate coefficients forms a subband required for next-level computation. The coefficients are computed in a serial manner and reordering of intermediate coefficients reduce not only the memory elements but also the circuit complexity. The proposed pipelined architecture reduces the requirement of memory elements by 50%. Furthermore, the hardware implementation results show that the area and power requirement are reduced by 33% and 20%, respectively.