Experimental Assessment of Multilevel RRAM-Based Vector-Matrix Multiplication Operations for In-Memory Computing
- Resource Type
- Periodical
- Authors
- Quesada, E.P.; Mahadevaiah, M.K.; Rizzi, T.; Wen, J.; Ulbricht, M.; Krstic, M.; Wenger, C.; Perez, E.
- Source
- IEEE Transactions on Electron Devices IEEE Trans. Electron Devices Electron Devices, IEEE Transactions on. 70(4):2009-2014 Apr, 2023
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Virtual machine monitors
Logic gates
Programming
Random access memory
Voltage measurement
Nonvolatile memory
Monitoring
In-memory computing (IMC)
multilevel
resistive random access memory (RRAM)
vector-matrix multiplication (VMM)
- Language
- ISSN
- 0018-9383
1557-9646
Resistive random access memory (RRAM)-based hardware accelerators are playing an important role in the implementation of in-memory computing (IMC) systems for artificial intelligence applications. The latter heavily rely on vector-matrix multiplication (VMM) operations that can be efficiently boosted by RRAM devices. However, the stochastic nature of the RRAM technology is still challenging real hardware implementations. To study the accuracy degradation of consecutive VMM operations, in this work we programed two RRAM subarrays composed of $8\times $ 8 one-transistor-one-resistor (1T1R) cells following two different distributions of conductive levels. We analyze their robustness against 1000 identical consecutive VMM operations and monitor the inherent devices’ nonidealities along the test. We finally quantize the accuracy loss of the operations in the digital domain and consider the trade-offs between linearly distributing the resistive states of the RRAM cells and their robustness against nonidealities for future implementation of IMC hardware systems.