With the advancement of circuit generations, architectures and technology nodes progressing to smaller and smaller transistor sizes; a decrease in the thickness of the BEoL layers of these integrated circuits (IC) is also occurring. In addition, mature older technology nodes have also experienced product life cycle extensions through the integration of new upgrade enhancements that are closely associated with a decrease in a layer or layers of its respective BEoL dielectric stack [1]. Typically heavy focus is placed on the in-plane X and Y dimensions of these shrinking materials and features. They are closely examined, studied and modelled with respect to the crackstop's robustness and strength. These X and Y dimensions are diligently monitored and honed to ensure that crackstop integrity and strength are not compromised by the decreasing dimensional sizes employed. However, associated with these X and Y reductions in size is an often overlooked Z dimension or thickness. While the X and Y dimensions are manipulatable with respect to a crackstop's design; the Z dimensional thickness is often locked and unalterable having been dictated by the various manufacturing processes employed to construct the respective individual BEoL layers. 3D FEM models have been constructed to investigate how thickness changes alter the overall mechanical strength and integrity of the IC's protective crackstop barrier and consequently its effectiveness and ultimately its performance at preventing crack growth and propagation from breaching into an IC's active prime region. These investigations found that the dielectric thickness reductions occurring beyond the 14nm technology standard, increases the probability of the crack development and propagation significantly.