Sample synchronization of multiple multiplexed DA and AD converters in FPGAs
- Resource Type
- Conference
- Authors
- Ohlemueller, Thilo; Petri, Markus
- Source
- 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2011 IEEE 14th International Symposium on. :301-304 Apr, 2011
- Subject
- Components, Circuits, Devices and Systems
Computing and Processing
Clocks
Field programmable gate arrays
Synchronization
Multiplexing
Phase locked loops
Hardware
Routing
- Language
In this paper we investigate the problem of multiple multiplexing DA and AD converters in respect to the sample synchronicity. Different proposals for solution are presented. We show a method to synchronize multiple multiplexed high speed DA and AD converters in FPGAs. The method determines the phase difference between the data clocks of two DA/AD converters, but avoids shifting the input/output data and dealing with multiple clock domains. Specific hardware setup and FPGA implementation details are analyzed and taken into account as well.