A 112-Gb/s —8.2-dBm Sensitivity 4-PAM Linear TIA in 16-nm CMOS With Co-Packaged Photodiodes
- Resource Type
- Periodical
- Authors
- Patel, D.; Sharif-Bakhtiar, A.; Carusone, T.C.
- Source
- IEEE Journal of Solid-State Circuits IEEE J. Solid-State Circuits Solid-State Circuits, IEEE Journal of. 58(3):771-784 Mar, 2023
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Computing and Processing
Optical receivers
Inverters
Optical switches
Costs
Optical signal processing
Integrated circuit interconnections
Gain
100 Gb/s
400 GbE
CMOS
co-packaged optical receiver front end
continuous-time linear equalizer (CTLE)
fin field effect transistor (FinFET)
gigabit Ethernet
inverter
low-noise broadband amplifier
optical communications
PAM-4
transimpedance amplifier (TIA)
- Language
- ISSN
- 0018-9200
1558-173X
A flip-chip co-packaged linear transimpedance amplifier (TIA) in 16-nm fin field effect transistor (FinFET) CMOS demonstrating 112-Gb/s four-level pulse-amplitude modulation (4-PAM) with −8.2-dBm sensitivity is presented in support for optical receivers required in the next-generation intra-data center links. A proposed three-stage TIA is comprised of a shunt-feedback stage followed by digitally programmable continuous-time linear equalizers (CTLEs) and a variable gain amplifier (VGA). Broadband low-noise design is achieved by having the first stage with much lower bandwidth (BW) followed by the proposed BW recovering CTLEs. A low-power design is supported by the inverter-based single-ended architecture with a single-ended-to-pseudo-differential conversion in the last stage. TIA’s BW extension is further supported by optimizing the photodiode-to-receiver (PD-to-RX) interconnect and utilizing several inductive peaking techniques. It achieves 63-dB $\Omega $ gain, 32-GHz BW, and an average input-referred current noise density of 16.9 pA/ $\sqrt {\text {Hz}}$ while operating at 0.9-V supply and consuming 47-mW power. Opto-electrical measurements are performed on a co-packaged prototype comprised of identical proposed TIAs in CMOS with combinations of various commercial PDs and PD-to-RX interconnect lengths confirming 112-Gb/s 4-PAM reception meeting pre-forward error correction (FEC) symbol error rate (SER) of $4.8 \times 10 ^{-4}$ without any post-equalization.