This paper presents a new wide fan-in domino OR-gate for high speed VLSI circuits with reduced power dissipation, lowered process variations and enhanced noise margin. In this work, some crucial modifications in evaluation network are done to increase the threshold voltage of PDN transistors in standby mode using stacking phenomenon hence reduction in the power dissipation of the proposed domino. Further, Noise immunity is also enhanced by overcoming the charge sharing problem. The idea used in this work is to effectively turn ON and OFF the keeper transistor so that overall power can be saved. The simulations are done under cadence virtuoso environment for wide fan-in (8, 16, 32 and 64-input) OR-gates using 45nm CMOS technology node at 1V power supply and 1GHz clock frequency respectively. The simulation results i.e. noise margin, average power, and standard deviation, show 29%, 21% and 32% improvements respectively in the proposed work as compared to standard domino gate.