An adaptive frame rate imager suitable for integration in a wireless IoT device is developed. Fine-grained power management working with adaptive frame functionality reduces power consumption proportional to the frame rate. An analog processing chain employing telescopic OTA with a common mode shift technique is developed to achieve a low power design while maintaining 9-bit accuracy noise and settling error. The OTA operates in a time-sharing DDR regime that halves the power consumption. A hierarchical column multiplexer and variable capacitance buffer are introduced to minimize the capacitive load of the OTA. The imager consumes 1.51 mW in 15-fps mode, reducing power by 33% compared with the maximum frame rate of 51 fps. A 372×316, 5-µm pixel array, readout circuit, ADC, and LDO are fully integrated into a 2.86 mm × 2.58 mm chip to reduce the dimensions of an image acquisition system.