A Bi-stable 1- /2-Transistor SRAM in 14 nm FinFET Technology for High Density / High Performance Embedded Applications
- Resource Type
- Conference
- Authors
- Widjaja, Yuniarto; Wilson, James; Nguyen, Tu; Han, Jin-Woo; Norwood, Christopher; Maheshwari, Dinesh; Lai, Stefan; Vorenkamp, Pieter; Or-Bach, Zvi; Nishi, Yoshio
- Source
- 2018 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2018 IEEE International. :18.6.1-18.6.4 Dec, 2018
- Subject
- Components, Circuits, Devices and Systems
Random access memory
FinFETs
Standards
Current measurement
Temperature measurement
Leakage currents
- Language
- ISSN
- 2156-017X
1-transistor and 2-transistor (1T/2T) SRAM are fabricated using 14 nm baseline foundry process without any process modifications. A bi-stable self-latch mechanism is established in a single transistor where its p-type body becomes electrically floating by reverse biased, buried depletion regions from adjacent n-wells. The bit cell operation and the disturb immunity are verified. A unit cell size of $0.039\ \mu \mathrm{m}^{2}$ is achieved, offering >2x area reduction over 6T-SRAM and providing comparable power and performance.