0.1-/spl mu/m CMOS technology for high-speed logic and system LSIs with SiO/SiN/poly-Si/W gate-system
- Resource Type
- Conference
- Authors
- Onai, T.; Tsujikawa, S.; Uchino, T.; Tsuchiya, R.; Ohnishi, K.; Fukuda, H.; Hisamoto, D.; Yamamoto, N.; Yugami, J.; Ichinose, K.; Ootsuka, F.
- Source
- International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318) Electron devices Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International. :937-939 1999
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Photonics and Electrooptics
CMOS logic circuits
CMOS technology
Large scale integration
Silicon compounds
Tunneling
Electrodes
Dielectrics
MOS devices
Boron
Contact resistance
- Language
0.1-/spl mu/m CMOS devices for high speed logic and system LSIs have been successfully achieved. The device has an SiO/SiN stacked gate dielectric with T/sub oxinv/=2.8 nm to avoid gate direct tunneling leakage and boron penetration. It also utilizes a poly/metal stacked gate electrode to reduce gate resistance. Carefully optimized source/drain extensions and punch-through stoppers offer good short channel operation below 0.1-/spl mu/m gate length and high-drive currents of 1000 /spl mu/A//spl mu/m for NMOSs and 410 /spl mu/A//spl mu/m for PMOSs at 1.5 V voltage supply.