A novel 0.20 /spl mu/m full CMOS SRAM cell using stacked cross couple with enhanced soft error immunity
- Resource Type
- Conference
- Authors
- Ootsuka, F.; Nakamura, M.; Miyake, T.; Iwahashi, S.; Ohira, Y.; Tamaru, T.; Kikushima, K.; Yamaguchi, K.
- Source
- International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217) Electron devices - IEDM 1998 Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International. :205-208 1998
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Photonics and Electrooptics
Random access memory
Capacitors
Error correction codes
CMOS process
Coupling circuits
Integrated circuit interconnections
Capacitance
BiCMOS integrated circuits
Error correction
Voltage
- Language
- ISSN
- 0163-1918
An SRAM cell is proposed, in which additional capacitance is formed between the two local interconnects which are used for cross couple wiring. This novel cell with stacked cross couple (SCC) has an advantage in reducing the cell area to 80% of that of the conventional SRAM cell. Furthermore, the capacitor area can be enlarged to 40% of the cell area which enables one to adopt thick capacitor insulator. Reduction in capacitor leakage current by using plasma SiN with low Si-H concentration, and the device performances are also discussed.