Integration of manufacturable 65nm-node HfSiON transistors optimized with low-thermal-budget CMOS process
- Resource Type
- Conference
- Authors
- Mineji, A.; Tamura, Y.; Watanabe, T.; Ozaki, H.; Ootsuka, F.; Aoyama, T.; Shibata, K.; Tsujita, K.; Ohashi, N.; Yasuhira, M.; Arikado, T.
- Source
- IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004. Electron devices meeting Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International. :927-930 2004
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Photonics and Electrooptics
Manufacturing processes
CMOS process
Random access memory
Temperature
Gate leakage
High K dielectric materials
Crystallization
Silicon compounds
Annealing
Leakage current
- Language
This paper describes the 65nm-node HfSiON transistors that have been fully integrated to SRAM array. By optimizing the thermal process after the gate stack formation, the scaling of EOT has been attained without introducing additional high-k formation techniques. Highly manufacturable HfSiON transistors with the symmetrical Vth values suitable for SRAM operation at 1.1V power supply are demonstrated.