Designing of Multiplexer and De-Multiplexer Using Different Adiabatic Logic in 90nm Technology
- Resource Type
- Conference
- Authors
- Mittal, Deepak; Niranjan, Amit
- Source
- 2018 9th International Conference on Computing, Communication and Networking Technologies (ICCCNT) Computing, Communication and Networking Technologies (ICCCNT), 2018 9th International Conference on. :1-7 Jul, 2018
- Subject
- Communication, Networking and Broadcast Technologies
Computing and Processing
Geoscience
Robotics and Control Systems
Signal Processing and Analysis
Adiabatic
Multiplexing
MOSFET
Clocks
MOSFET circuits
Power dissipation
Adiabatic Logic
Dual Sleep technique
energy efficiency
2N2P Logic
2N2N2P logic
- Language
In this research paper we represented the design and evaluation of 8:1 Multiplexer using different adiabatic logics. For VLSI design engineers, high power consumption is the main factor in digital circuits. In this paper we are going to presents the CMOS-logic based new design in 90 nm technology for a low power and high speed adiabatic 8:1 Multiplexer and De-Multiplexer for following this trend. In which we focus on the characteristics of the CMOS and adiabatic logic families 2N2P, 2N-2N2P use a cross-coupled transistor structure for adiabatic operation and dual sleep approach. Normally Adiabatic logic families use multiphase clocks. Multiphase clock increases power dissipation on their clock distribution network. Some adiabatic logics are not effective for high speed operating design due to their clock skew issues and high complexity because of multiphase clocks. So in this research paper we are focusing on energy recovery with efficient power clock power consumption.