A 1Tb 3b/Cell 3D-Flash Memory of more than 17Gb/mm2 bit density with 3.2Gbps interface and 205MB/s program throughput
- Resource Type
- Conference
- Authors
- Sako, M.; Nakajima, T.; Kono, F.; Nakano, T.; Fujiu, M.; Musha, J.; Nakamura, D.; Kanagawa, N.; Shimizu, Y.; Yanagidaira, K.; Utsumi, T.; Kawano, T.; Hosomura, Y.; Yabe, H.; Kano, M.; Sugawara, H.; Sravan, A. H.; Hayashi, K.; Kouchi, T.; Watanabe, Y.
- Source
- 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) VLSI Technology and Circuits (VLSI Technology and Circuits), 2023 IEEE Symposium on. :1-2 Jun, 2023
- Subject
- Components, Circuits, Devices and Systems
Wiring
Degradation
Very large scale integration
Throughput
Sensors
Decoding
3D-Flash Memory
unmatched DQS
Row decoder
Sense amplifier
- Language
- ISSN
- 2158-9682
A 210 + WL layers 1Tb 3b/cell 3D-Flash Memory achieves the high bit density of $\gt17$ Gb/mm 2 . Physical 8plane architecture realizes low read latency of 40us and high program throughput of 205MB. High interface speed of 3.2Gbps is accomplished by reducing DQ area in the X direction to 41%. Hybrid row address decoders (X-DEC) can deal with the wiring congestion issue caused by the new architecture, minimizing the read latency degradation. One-pulse-two-strobe technique reduces sensing time by 18% and contributes to the achievement of 205MB/s program throughput.