The intrinsic gate resistance ( ${R}_{\text {g}{\_}{\text {in}}}{)}$ , which is a novel resistance factor embedded in transistors, was determined for silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFETs). The study demonstrated that ${R}_{\text {g}{\_}{\text {in}}}$ is overestimated in the conventional measurement scheme due to the contact resistance ${R}_{\text {sp}}$ between p-type SiC and the source electrode. Here, 6.7 $\text{m}\Omega \cdot $ cm2 was measured for ${R}_{\text {sp}}$ using the transfer length method (TLM), and ${R}_{\text {g}{\_}{\text {in}}}$ = $9 \Omega $ was the revised value, unlike the conventional value of $25 \Omega $ . This improved ${R}_{\text {g}{\_}{\text {in}}}$ provides better-simulated switching waveforms in a double-pulse test (DPT) with a SiC MOSFET; however, the method requires detailed knowledge of the target device. Accordingly, we developed another measurement scheme without such prerequisites. In this scheme, three types of impedance ( ${Z}{)}$ were measured: ${Z}$ between the drain (D) and source terminal (S), and two ${Z}_{\text {s}}$ between the gate and S, with DS left open and short. From these results, ${R}_{\text {g}{\_}{\text {in}}}$ was determined to be $8.8 \Omega $ with other device parasitic parameters simultaneously.