Junctionless transistors (JLTs) have promising advantages such as structural simplicity without p-n-junctions and bulk conduction-based operation for the realization of advanced complementary metal oxide semiconductor (CMOS) technologies. Here the channel-length dependence on the operation of JLTs with substrate biasing ( ${V}_{\text {gb}}$ ) was investigated in detail. Parasitic series resistance ( ${R}_{\text {sd}}$ ) noticeably decreased as ${V}_{\text {gb}}$ increased. In addition, transconductance ( ${g}_{\text {m}}$ ), its derivative ( dg m / dV gf ), and ON-drain current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) in a short-channel JLT were significantly affected by the ${V}_{\text {gb}}$ -modulated ${R}_{\text {sd}}$ with charge coupling effects. This work provides important information for better understanding and true estimation of intrinsic JLT performance, for practical applications based on polycrystalline Si, III–V semiconductors, and transition metal dichalcogenides (TMDs) nano-materials as well as advanced logic devices.