Modeling of parallel electric field tunnel FETs
- Resource Type
- Conference
- Authors
- Fukuda, K.; Morita, Y.; Mori, T.; Mizubayashi, W.; Masahara, M.; Yasuda, T.; Migita, S.; Ota, H.
- Source
- 2015 International Workshop on Computational Electronics (IWCE) Computational Electronics (IWCE), 2015 International Workshop on. :1-4 Sep, 2015
- Subject
- Components, Circuits, Devices and Systems
Computing and Processing
Photonics and Electrooptics
Logic gates
Semiconductor process modeling
Electric fields
Yttrium
Field effect transistors
Silicon
Semiconductor device modeling
tunnel FET
device simulation
epitaxial layer
modeling
tunnel path
- Language
Tunnel FETs with vertical tunnel paths are fabricated and successfully modeled by the nonlocal band to band tunneling model. Although enhancement of ON currents are obtained by longer source gate overlap lengths, the increase of the ON current is less than proportional to the overlap lengths, because of non-uniformity of the band to band tunneling generation rates. The behavior of this type of tunnel FETs is precisely explained by the device simulation model. The key point is the peak generation rates at the source edge.