A 24–72-GS/s 8-b Time-Interleaved SAR ADC With 2.0–3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET
- Resource Type
- Periodical
- Authors
- Kull, L.; Luu, D.; Menolfi, C.; Brandli, M.; Francese, P.A.; Morf, T.; Kossel, M.; Cevrero, A.; Ozkaya, I.; Toifl, T.
- Source
- IEEE Journal of Solid-State Circuits IEEE J. Solid-State Circuits Solid-State Circuits, IEEE Journal of. 53(12):3508-3516 Dec, 2018
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Computing and Processing
Bandwidth
Clocks
Capacitance
Capacitors
FinFETs
Resistance
Electrostatic discharges
Analog-to-digital converter (ADC)
asynchronous
bandwidth
interleaver
sampling
successive approximation (SAR)
time-interleaved
- Language
- ISSN
- 0018-9200
1558-173X
A 24–72-GS/s 8-b time-interleaved analog-to-digital converter (ADC) is presented which exceeds 39-dB SNDR at low input frequency and 30-dB SNDR at Nyquist. High SNDR at Nyquist is achieved by 16 parallel sampling switches driven by short clock pulses. Clock-pulse edges can be shifted digitally to reduce the impact of timing mismatch. A total of 64 asynchronous 8-b successive approximation (SAR) ADCs at low supply voltage convert sampled voltages. The SAR ADCs use a differential capacitive DAC, one comparator per decision, and include a reference voltage DAC and buffer. The ADC consumes 2.0 pJ/conversion at 48 GS/s and 3.3 pJ/conversion at 72 GS/s and is implemented in 14-nm CMOS FinFET on 0.15 mm 2 .