A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET
- Resource Type
- Periodical
- Authors
- Ozkaya, I.; Cevrero, A.; Francese, P.A.; Menolfi, C.; Morf, T.; Brandli, M.; Kuchta, D.M.; Kull, L.; Baks, C.W.; Proesel, J.E.; Kossel, M.; Luu, D.; Lee, B.G.; Doany, F.E.; Meghelli, M.; Leblebici, Y.; Toifl, T.
- Source
- IEEE Journal of Solid-State Circuits IEEE J. Solid-State Circuits Solid-State Circuits, IEEE Journal of. 53(4):1227-1237 Apr, 2018
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Computing and Processing
Clocks
Delays
Decision feedback equalizers
Integrated circuit modeling
Analytical models
Transfer functions
Jitter
Clock and data recovery (CDR)
decision feedback equalization (DFE)
I/O link
non-return to zero (NRZ)
optical receiver (RX)
phase rotator (PR)
RX
self-timed comparator
sensitivity
shunt feedback
transimpedance amplifier (TIA)
variable gain amplifier (VGA)
- Language
- ISSN
- 0018-9200
1558-173X
This paper presents an analysis on the loop dynamics of the digital clock and data recovery (CDR) circuits and the design details of a non-return to zero optical receiver (RX) in a 14-nm bulk CMOS finFET technology with high jitter tolerance (JTOL) performance, which is designed based on the analysis. The digital CDR logic is designed full custom in order to keep it running at a quarter rate clock of 15 GHz at 60-Gb/s sampling speed to minimize the CDR loop latency. The RX is characterized in a vertical cavity surface emitting laser-based link recovering a 7-bit pseudo-random bit sequence bit pattern at 60 Gb/s with a JTOL corner frequency of around 80 MHz while maintaining an energy efficiency of 1.9 pJ/bit.