A simple electrical method for etch bias and process reliability determination
- Resource Type
- Conference
- Authors
- Yiang, Kok-Yong; Chin, Melida; Marathe, Amit; Aubel, Oliver
- Source
- 2010 IEEE International Reliability Physics Symposium Reliability Physics Symposium (IRPS), 2010 IEEE International. :562-565 May, 2010
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Fields, Waves and Electromagnetics
Power, Energy and Industry Applications
Etching
CMOS technology
Testing
Dielectric breakdown
Chemical technology
Electric breakdown
Monitoring
Lithography
Samarium
Reliability engineering
Etch bias
line-edge roughness (LER)
VRDB
- Language
- ISSN
- 1541-7026
1938-1891
A fast and simple electrical method is developed to characterize the etch bias and post-patterned ILD breakdown strength of back-end-of-line (BEOL) interconnects, as well as the middle-of-line (MOL) contact/poly module. The method provides a timely and valuable monitoring mechanism for assessing lithography, etch, thin-film quality and process reliability windows.