3-D Logic Circuit Design-Oriented Electrothermal Modeling of Vertical Junctionless Nanowire FETs
- Resource Type
- Periodical
- Authors
- Mannaa, S.; Poittevin, A.; Marchand, C.; Deleruyelle, D.; Deveautour, B.; Bosio, A.; O'Connor, I.; Mukherjee, C.; Wang, Y.; Rezgui, H.; Deng, M.; Maneux, C.; Muller, J.; Pelloquin, S.; Moustakas, K.; Larrieu, G.
- Source
- IEEE Journal on Exploratory Solid-State Computational Devices and Circuits IEEE J. Explor. Solid-State Comput. Devices Circuits Exploratory Solid-State Computational Devices and Circuits, IEEE Journal on. 9(2):116-123 Dec, 2023
- Subject
- Components, Circuits, Devices and Systems
Computing and Processing
Temperature measurement
Integrated circuit modeling
Mathematical models
Logic circuits
Nanowires
Three-dimensional integrated circuits
Logic design
3-D electronics
compact model
electrothermal modeling
logic circuit design
vertical nanowire (NW) transistor
- Language
- ISSN
- 2329-9231
This work presents new insights into 3-D logic circuit design with vertical junctionless nanowire FETs (VNWFET) accounting for underlying electrothermal phenomena. Aided by the understanding of the nanoscale heat transport in VNWFETs through multiphysics simulations, the SPICE-compatible compact model captures temperature and trapping effects principally through a shift of the device threshold voltage. Circuit-level simulations indicate a strong impact of temperature variation on functionality and figures of merits, such as energy-delay products. Subsequent guidelines for design considerations are discussed that are intended to provide feedback for technology improvements.