A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs
- Resource Type
- Conference
- Authors
- Luo, Pei-Wen; Chen, Chi-Kang; Sung, Yu-Hui; Wu, Wei; Shih, Hsiu-Chuan; Lee, Chia-Hsin; Lee, Kuo-Hua; Li, Ming-Wei; Lung, Mei-Chiang; Lu, Chun-Nan; Chou, Yung-Fa; Shih, Po-Lin; Ke, Chung-Hu; Shiah, Chun; Stolt, Patrick; Tomishima, Shigeki; Kwai, Ding-Ming; Rong, Bor-Doou; Lu, Nicky; Lu, Shih-Lien; Wu, Cheng-Wen
- Source
- 2015 Symposium on VLSI Circuits (VLSI Circuits) VLSI Circuits (VLSI Circuits), 2015 Symposium on. :C186-C187 Jun, 2015
- Subject
- Components, Circuits, Devices and Systems
Photonics and Electrooptics
Power, Energy and Industry Applications
Random access memory
Through-silicon vias
Bandwidth
Arrays
Three-dimensional displays
Energy efficiency
Performance evaluation
- Language
- ISSN
- 2158-5601
2158-5636
Presented is a novel half Gb DRAM device for 3D stacked systems utilizing TSV. It is designed through the use of a new computer-aided design methodology and which realizes 819 Gb/s bandwidth across 16 channels and