Gate-to-drain/source overlap and asymmetry effects on hot-carrier generation
- Resource Type
- Conference
- Authors
- Devoge, P.; Aziza, H.; Lorenzini, P.; Masson, P.; Julien, F.; Marzaki, A.; Malherbe, A.; Delalleau, J.; Cabout, T.; Regnier, A.; Niel, S.
- Source
- 2022 IEEE International Integrated Reliability Workshop (IIRW) Integrated Reliability Workshop (IIRW), 2022 IEEE International. :1-5 Oct, 2022
- Subject
- Components, Circuits, Devices and Systems
Medium voltage
Logic gates
Hot carrier effects
Impact ionization
Semiconductor process modeling
Numerical models
Transistors
transistor
device
CMOS
reliability
hot-carrier
overlap length
asymmetry
TCAD
substrate current
- Language
- ISSN
- 2374-8036
An investigation of the effects of gate-to-drain/source overlap length and overlap asymmetry on the electrical and hot-carrier generation behavior is conducted on a medium-voltage (around 3 to 5 V) transistor in a 40 nm CMOS technology, using TCAD simulations calibrated with electrical measurements. The substrate current versus gate voltage is used to monitor the hot-carrier impact ionization rate. A novel numerical approach of decomposing the substrate current into its drain-side and source-side constituents is proposed, allowing to determine the junction where most of the impact ionization occurs depending on the geometrical and electrical parameters.