A New High Density 3D Stackable Via RRAM for Computing-in-Memory SOC Applications
- Resource Type
- Periodical
- Authors
- Sing, S.; Wang, Y.; Lin, W.; Chih, Y.; King, Y.; Lin, C.J.
- Source
- IEEE Transactions on Electron Devices IEEE Trans. Electron Devices Electron Devices, IEEE Transactions on. 71(4):2399-2403 Apr, 2024
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Three-dimensional displays
Latches
Logic gates
Resistance
Voltage
Layout
Common Information Model (computing)
Artificial synapse
CMOS logic
computing-in-memory (CIM)
multiply–accumulate (MAC)
neural network (NN)
resistive random access memory (RRAM)
- Language
- ISSN
- 0018-9383
1557-9646
A novel 3D stackable Via resistive random access memory (RRAM) latch and Via RRAM logic gates implemented in 16-nm FinFET logic process for computing-in-memory (CIM) applications are proposed. Via RRAM latch array can provide more than 60 Mb/mm2 of latch storage density to achieve stable full-swing high-speed output. By simplifying the readout circuit, latch array allows flexible configuration in advanced SOC. Three-Dimensional Via RRAM logic gates compute the stored data internally. The features show a promising way to reduce the von Neumann bottleneck.