A 1.93TOPS/W Deep Learning Processor with a Reconfigurable Processing Element Array Based on SRAM Access Optimization
- Resource Type
- Conference
- Authors
- Chen, Liao-Chuan; Li, Zhaofang; Lin, Yi-Jhen; Lee, Kuan-Pei; Tang, Kea-Tiong
- Source
- 2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) Circuits and Systems (APCCAS), 2022 IEEE Asia Pacific Conference on. :15-19 Nov, 2022
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
General Topics for Engineers
Deep learning
Power demand
Random access memory
Optimization methods
Parallel processing
Energy efficiency
Spatial databases
convolutional neural network (CNN)
energy efficiency
accelerator
data movement
- Language
Deep convolutional neural networks feature numerous parameters, causing data movement to usually dominate the power consumed when computing inferences. This paper proposes an on-chip buffer access optimization method and high-data-reuse architecture that can reduce the power consumed by an on-chip buffer by up to 67.8%. The chip is designed in a TSMC 40 nm process running at 200 MHz and achieves energy efficiency of 1.93 TOPS/W.