Numerical Studies and Validation of Experimental Pentacene Transistor Characteristics
- Resource Type
- Conference
- Authors
- Boujnah, Aicha; Boubaker, Aimen; Kalboussi, Adel; Li, Shou; Lmimouni, Kamal
- Source
- 2019 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS) Design & Test of Integrated Micro & Nano-Systems (DTS), 2019 IEEE International Conference on. :1-4 Apr, 2019
- Subject
- Components, Circuits, Devices and Systems
Dielectrics
Logic gates
Pentacene
OFETs
Microelectronics
Threshold voltage
SlLVACO
organic transistor OFET
dielectric thickness
threshold voltage
mobility
Ion/Ioff
- Language
This paper present a numerical validation of experimental results of Bottom Gate/Bottom Contact Pentacene transistor using SILVACO ATLAS simulator. We investigated the impact of different gate dielectric thickness on transistor performance and we estimated threshold voltage Vth, current ratio I on /I off and saturation mobility μ values. We found that gate dielectric thickness is proportional to Vth and inversely proportional to μ.