Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis
- Resource Type
- Periodical
- Authors
- Lerner, S.; Taskin, B.
- Source
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems IEEE Trans. VLSI Syst. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on. 27(1):1-10 Jan, 2019
- Subject
- Components, Circuits, Devices and Systems
Computing and Processing
Merging
Clocks
Delays
Wires
Mathematical model
Degradation
Bounded skew
bounded slew
clock tree synthesis (CTS)
merging region
slew merging region
- Language
- ISSN
- 1063-8210
1557-9999
Building clock trees for tight skew constraints of clock delivery networks is standard in the industry. Tight slew constraints of high-performance designs require post-processing techniques to satisfy slew constraints after clock tree synthesis (CTS). Post-processing adversely impacts the power dissipation. This paper proposes slew merging region CTS (SMRcts); a novel algorithm to satisfy bounded slew and skew constraints simultaneously during synthesis. Experimental results performed on International Symposium on Physical Design (ISPD) 2010 benchmarks using a 20-nm FinFET technology show an average reduction of 15% power over a bounded skew approach. Comparison to the ISPD 2010 CTS contest solutions in the literature shows SMRcts producing a 51% improvement in a utility metric. Scalability of SMRcts is demonstrated on ISPD 2013 benchmarks with up to 100k sinks.