A 2Gb/s/pin 512Mb Graphics DRAM with NoiseReduction Techniques
- Resource Type
- Conference
- Authors
- Brox, M.; Fibranz, H.; Kuzmenka, M.; Lu, F.; Mann, S.; Markert, M.; Moller, U.; Plan, M.; Schiller, K.; Schmolz, P.; Schrogmeier, P.; Tuber, A.; Weber, B.; Mayer, P.; Spirkl, W.; Steffens, H.; Weller, J.
- Source
- 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International. :537-546 2006
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Graphics
Random access memory
Voltage
Parasitic capacitance
Resonance
Propagation delay
MOS devices
Acceleration
Bandwidth
Jitter
- Language
- ISSN
- 0193-6530
2376-8606
A 512Mb DRAM operates up to a data-rate of 2Gb/s/pin. It employs an averaging pad-driver design which reduces simultaneous switching noise to one third of a conventional design. Resistive damping elements eliminate the level degradation of the receivers caused by an oscillation of the on-chip ground. A technique for cancelling line-to-line coupling noise is also described