Simulator-independent capacitance macro model for power DMOS transistors
- Resource Type
- Conference
- Authors
- Pawel, S.; Kusano, H.; Nakamura, Y.; Teich, W.; Terashima, T.; Netzel, M.
- Source
- ISPSD '03. 2003 IEEE 15th International Symposium on Power Semiconductor Devices and ICs, 2003. Proceedings. Power semiconductor devices and IC's Power Semiconductor Devices and ICs, 2003. Proceedings. ISPSD '03. 2003 IEEE 15th International Symposium on. :287-290 2003
- Subject
- Power, Energy and Industry Applications
Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Voltage
SPICE
Parasitic capacitance
Power system modeling
Cities and towns
Circuit simulation
Capacitance measurement
Driver circuits
Europe
Large scale integration
- Language
The paper presents an easy-to-use macro model for the gate-drain and gate-source capacitances of power DMOS transistors in VLSI smart power technologies according to T. Terashima (2002). The model is a capacitance model which can be used as an add-on to any existing DC SPICE model and with any SPICE simulator and can be derived directly form measurement data.