CMOS ADCs Towards 100 GS/s and Beyond
- Resource Type
- Conference
- Authors
- Kull, Lukas; Luu, Danny; Francese, Pier Andrea; Menolfi, Christian; Braendli, Matthias; Kossel, Marcel; Morf, Thomas; Cevrero, Alessandro; Oezkaya, Ilter; Yueksel, Hazar; Toifl, Thomas
- Source
- 2016 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Compound Semiconductor Integrated Circuit Symposium (CSICS), 2016 IEEE. :1-4 Oct, 2016
- Subject
- Aerospace
Bioengineering
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Fields, Waves and Electromagnetics
Photonics and Electrooptics
Power, Energy and Industry Applications
Bandwidth
Clocks
Capacitors
Frequency measurement
Jitter
Resistors
FinFETs
- Language
- ISSN
- 2374-8443
The implementation of a 64x time-interleaved ADC in 32nm CMOS SOI is analyzed. Measurement results confirm 33 dB SNDR up to 19.9 GHz at 90 GS/s and 1.2V supply. Architecture details and analysis show insights into limitations and potentials of the chosen architecture. In par-ticular the input bandwidth is of concern for ADCs at more than 64 GS/s, as a larger number of sampling switches in-creases the parasitic load and reduces the input bandwidth. Insights on a simplified analysis of interleaver structures and existing solutions to bandwidth issues are highlighted and show a path to extend the sampling speed of CMOS ADCs beyond 100 GS/s.