Fabrication of 50-nm gate SOI n-MOSFETs using novel plasma-doping technique
- Resource Type
- Periodical
- Authors
- Won-Ju Cho; Chang-Geun Ahn; Kiju Im; Jong-Heon Yang; Jihun Oh; In-Bok Baek; Seongjae Lee
- Source
- IEEE Electron Device Letters IEEE Electron Device Lett. Electron Device Letters, IEEE. 25(6):366-368 Jun, 2004
- Subject
- Engineered Materials, Dielectrics and Plasmas
Components, Circuits, Devices and Systems
Fabrication
MOSFET circuits
Plasma temperature
Plasma immersion ion implantation
Doping
Silicon on insulator technology
Plasma sources
Annealing
Ion implantation
Lithography
- Language
- ISSN
- 0741-3106
1558-0563
A plasma-doping technique for fabricating nanoscale silicon-on-insulator (SOI) MOSFETs has been investigated. The source/drain (S/D) extensions of the tri-gate structure SOI n-MOSFETs were formed by using an elevated temperature plasma-doping method. Even though the activation annealing after plasma doping was excluded to minimize the diffusion of dopants, which resulted in a laterally abrupt S/D junction, we obtained a low sheet resistance of 920 /spl Omega///spl square/ by the elevated temperature plasma doping of 527 /spl deg/C. A tri-gate structure silicon-on-insulator n-MOSFET with a gate length of 50 nm was successfully fabricated and revealed suppressed short-channel effects.