Reduced-latency architecture for image smoothing exponential filters
- Resource Type
- Conference
- Authors
- Hassan, Firas; Pax, Nathan; Khorbotly, Sami
- Source
- 2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS) Circuits and Systems (MWSCAS), 2015 IEEE 58th International Midwest Symposium on. :1-4 Aug, 2015
- Subject
- Bioengineering
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Fields, Waves and Electromagnetics
General Topics for Engineers
Photonics and Electrooptics
Robotics and Control Systems
Signal Processing and Analysis
Finite impulse response filters
Hardware
IIR filters
Gabor filters
Computer architecture
Registers
- Language
- ISSN
- 1548-3746
1558-3899
Smoothing filters are low pass filters commonly used to reduce the details levels in image processing. This work suggests the use of a special family of low pass filters, namely the linear-phase exponential filters to perform image smoothing. The linear-phase exponential filters are used because they can be recursively implemented, which results in significant hardware savings. This work's contribution is a novel architecture to efficiently implement those filters. The suggested architecture achieves symmetric extension with a reduced overall latency in the filtering process of M cycles, where M is the size of the symmetrically extended data. Simulation results show that the fixed-point implementation of the suggested architecture achieves high PSNR when compared to the floating-point implementation of the conventional non recursive FIR implementation of the same filter with pre-filtering symmetric extension. The suggested architecture requires a constant number of logic functions regardless of the filter size. Only the number of registers increases as a function with the size of the filter.