The circuit design of the synergistic processor element of a CELL processor
- Resource Type
- Conference
- Authors
- Takahashi, O.; Cook, R.; Cottier, S.; Dhong, S.H.; Flachs, B.; Hirairi, K.; Kawasumi, A.; Murakami, H.; Noro, H.; Oh, H.; Onish, S.; Pille, J.; Silberman, J.
- Source
- ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005. Computer Aided Design Computer-Aided Design, 2005. ICCAD-2005. IEEE/ACM International Conference on. :111-117 2005
- Subject
- Computing and Processing
Components, Circuits, Devices and Systems
Robotics and Control Systems
Circuit synthesis
Latches
CMOS logic circuits
CMOS technology
Ground penetrating radar
Programmable logic arrays
Clocks
Frequency
Design optimization
Delay
- Language
- ISSN
- 1092-3152
1558-2434
A 32b 4-way SIMD dual-issue synergistic processor element of a CELL processor is developed with 20.9 million transistors in 14.8mm/sup 2/ using a 90nm SOI technology. CMOS static gates implement the majority of the logic. Dynamic circuits are used in critical areas, occupying 19% of the nonSRAM area. ISA, microarchitecture and physical implementation are tightly coupled to achieve a compact and power efficient design. Correct operation has been observed up to 5.6GHz at 1.4V supply and 56/spl deg/C.