Voltage Surges by Backside ESD Impacts on IC Chip in Flip Chip Packaging
- Resource Type
- Conference
- Authors
- Wadatsumi, Takuya; Kawai, Kohei; Hasegawa, Rikuu; Miki, Takuji; Nagata, Makoto; Muramatsu, Kikuo; Hasegawa, Hiromu; Sawada, Takuya; Fukushima, Takahito; Kondo, Hisashi
- Source
- 2022 IEEE International Reliability Physics Symposium (IRPS) Reliability Physics Symposium (IRPS), 2022 IEEE International. :P14-1-P14-6 Mar, 2022
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Engineering Profession
Semiconductor device measurement
Voltage measurement
Packaging
Electrostatic discharges
Silicon
Flip-chip devices
Surges
Electrostatic discharge
Full-wave simulation
On-chip monitor
- Language
- ISSN
- 1938-1891
Voltage surges induced by electrostatic discharge (ESD) impacts on the backside of an integrated circuit (IC) chip in flip-chip packaging potentially causes reliability problems and even leads to malfunctioning. On-chip voltage waveform monitor circuits on its frontside evaluate the surge as high as 200 mV when ESD gun at 200 V is discharged to the Si substrate backside through the contact resistance of 5 kto the backside of a 350 µm thick Si substrate. The distribution of voltages over the frontside area of an IC chip is measured and explained with full-system level backside ESD simulation.