A noise reduction technique for divider-less fractional-N frequency synthesizer using phase-interpolation technique
- Resource Type
- Conference
- Authors
- Narayanan, Aravind Tharayil; Katsuragi, Makihiko; Nakata, Kengo; Terashima, Yuki; Okada, Kenichi; Matsuzawa, Akira
- Source
- 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC) Design Automation Conference (ASP-DAC), 2016 21st Asia and South Pacific. :5-6 Jan, 2016
- Subject
- Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Signal Processing and Analysis
Phase locked loops
Jitter
Phase noise
Frequency synthesizers
Power demand
Dynamic range
Analytical models
- Language
- ISSN
- 2153-697X
This paper proposes a noise reduction technique for divider-less fractional-N frequency synthesizer using phase-interpolation technique. The phase interpolator helps reduce the jitter introduced into the system by the multi-phase generation mechanism used for the fractional operation. The proposed frequency synthesizer is fabricated in 65nm CMOS process and it is capable of working at frequencies ranging from 4.3GHz to 4.9GHz. The measured close-in phase noise is −113dBc/Hz at an offset of 200kHz from the carrier with 3.3mW power consumption, which results in a FoM of −246dB.