This paper describes the results of evaluation and simulation modeling of the influence of a silicon substrate propagation disturbance on circuit operation in silicon-on-insulator BCD (BIPOLAR/CMOS/LDMOS) process. In the evaluation, the susceptibility of the Widlar bandgap voltage reference (BGR) to a disturbance propagating from the substrate is measured by direct RF power injection tests in the bare chip state. We found that the termination impedance between separation areas without circuit elements on the wafer (field area) and the circuit ground is effective in improving the immunity performance of the circuit against disturbances from the substrate. In simulation modeling, the substrate propagation model is extracted with simple RLCG elements from 2D chip layout data using SPICE analysis. This model enable us to simulate the BGR circuit response to a substrate disturbance injected from the disturbance injection area, assuming an on-chip LDMOS, up to a maximum forward power of 10 dBm.