Nowadays, convolutional neural networks (CNN) are developing in the direction of low-computation and high-precision lightweight algorithms. However, conventional accelerators cannot achieve high performance for lightweight algorithms. Network-on-Chip (NoC) can solve this problem because of its configurable on-chip dataflow and large on-chip bandwidth. In this paper, we propose a new dual-layer NoC-based CNN accelerator with an optimized router for edge computing. Furthermore, we design a loop unfolding and mapping scheme based on the NoC so that the accelerator architecture can adapt to the data delivery requirements of various CNN algorithms with strong algorithmic generality. Our design is based on the SMIC 40nm process, and the core area is 9 mm2. The experimental results on MobileNet and RepVGG show a peak performance of 51.2 GOPS. The power consumption is 301.7 mW, and the energy efficiency reaches 169.7 GOPS/W at 200 MHz.