A 40nm Analog-Input ADC-Free Compute-in-Memory RRAM Macro with Pulse-Width Modulation between Sub-arrays
- Resource Type
- Conference
- Authors
- Jiang, Hongwu; Li, Wantong; Huang, Shanshi; Yu, Shimeng
- Source
- 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) VLSI Technology and Circuits (VLSI Technology and Circuits), 2022 IEEE Symposium on. :266-267 Jun, 2022
- Subject
- Components, Circuits, Devices and Systems
Transient response
Quantization (signal)
Stars
Random access memory
Prototypes
Very large scale integration
Pulse width modulation
RRAM
CIM
PWM
ADC-free
- Language
- ISSN
- 2158-9682
This paper presents an ADC-free compute-in-memory (CIM) RRAM-based macro, exploiting the fully analog intra-/inter-array computation. The main contributions include: 1) a lightweight input-encoding scheme based on pulse-width modulation (PWM), which improves the compute throughput by ~7 times; 2) a fully analog data processing manner between sub-arrays without explicit ADCs, which does not introduce quantization loss and saves the power by a factor of 11.6. The 40nm prototype chip with TSMC RRAM achieves energy efficiency of 421.53 TOPS/W and compute efficiency of 360 GOPS/mm 2 (normalized to binary operation) at 100MHz.