In this paper, the design of a front-end for 1.5GSPS 12bit Pipelined ADC is presented. The front-end circuit consists of an input buffer circuit and a Track and Hold Amplifier (THA) circuit. A common mode voltage (V CM )stablizing technique is applied to improve stability of input buffer over process, voltage and temperature (PVT) variations. To boost high frequency performance, a high frequency small signal elimination technique using dummy transistors is applied to the THA circuit. To maximize high speed performance, best performance of 40nm devices is taken advantage of in the front-end circuit by a new set of supply power and ground suiting for thin oxide device. This work is implemented in 40nm CMOS process with a 1.8V power supply. The THA circuit exhibits 71dB SFDR and 10.25bit ENOB at 1.5 GHz.