A high-speed, low-power capacitive-coupling transceiver for wireless wafer-level testing systems
- Resource Type
- Conference
- Authors
- Kim, Gil-Su; Ikeuchi, Katsuyuki; Daito, Mutsuo; Takamiya, Makoto; Sakurai, Takayasu
- Source
- 2010 IEEE International 3D Systems Integration Conference (3DIC) 3D Systems Integration Conference (3DIC), 2010 IEEE International. :1-4 Nov, 2010
- Subject
- Fields, Waves and Electromagnetics
Computing and Processing
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Wireless communication
Testing
Transceivers
Bandwidth
Optical signal processing
Couplings
Integrated circuits
- Language
A high-speed, low-power capacitive-coupling transceiver is presented for wireless wafer-level testing systems. The proposed transceiver achieves the highest data rate of 15Gb/s in 65nm CMOS process which is 7.5 times higher than previous work. The parallel termination increases the signal bandwidth in a printed circuit board (PCB) by 8.5 times. The glitch signaling reduces the static power consumption of conventional nonreturn-to-zero (NRZ) signaling by 30%. These two design techniques lead to the lowest energy per bit of 0.47pJ/b in a chip-to-board communication.