A 0.75-5GHz Wide-Range 8-Phases Delay-Locked Loop With Low Noise Charge Pump
- Resource Type
- Conference
- Authors
- Taalab, Peter Gaied; Ibrahim, Sameh; Dessouky, Mohamed
- Source
- 2021 16th International Conference on Computer Engineering and Systems (ICCES) Computer Engineering and Systems (ICCES), 2021 16th International Conference on. :1-5 Dec, 2021
- Subject
- Bioengineering
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Robotics and Control Systems
Signal Processing and Analysis
Semiconductor device modeling
Charge pumps
Power measurement
Power demand
Phase measurement
Jitter
Delays
delay-locked loop
charge pump
low phase noise
wide-range
- Language
A 0.75-5GHz wide-range delay-locked loop (DLL) with a low noise charge pump is presented. A start-controlled circuit is used to avoid false locking. The DLL has 8-phases output clocks with a 45° phase difference, using a modified charge pump to reduce static phase error. This DLL has been designed in a 22nm CMOS process. The measured root-mean-square and peak-to-peak jitters are 0.5ps and 1.83ps at 5GHz, respectively. The power dissipation is 14.8mW for a supply voltage of 0.9V.