Time divided architecture for closed loop MEMS capacitive accelerometer
- Resource Type
- Conference
- Authors
- Huang, Jingqing; Zhang, Tingting; Zhao, Meng; Hong, Lichen; Zhang, Yacong; Lu, Wengao; Chen, Zhongjian; Hao, Yilong
- Source
- 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology Solid-State and Integrated Circuit Technology (ICSICT), 2012 IEEE 11th International Conference on. :1-3 Oct, 2012
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Mathematical model
Force
Integrated circuit modeling
Accelerometers
Electrostatics
MATLAB
- Language
This paper mainly discusses issues concerning the architecture of time divided closed loop accelerometer. For this particular architecture mathematical relationship between the external acceleration detected by sensor and the voltage output of the readout circuits is deduced. Both Matlab/Simulink model and Verilog-A model for such architecture are established. Simulation results agree with the mathematical formula. Readout circuits designed to work under 50kHz with feedback duty cycle η being 60% are fabricated using 0.35μm HV CMOS process. Test results show a sensitivity of 1.518V/g.