Combining Topological & Physical Pattern Recognition To Enhance Memory Chip Reliability
- Resource Type
- Conference
- Authors
- Hany, Sherif; Byun, Sunsoo; Sarhan, Hossam; Medhat, Dina; ElRefaee, Mohamed; Jang, Jaehyun; Jeong, Baekryong; Choi, Hyunseung; Choi, Sunmi; Muirhead, Jonathan; Hogan, Matthew
- Source
- 2020 IEEE International Integrated Reliability Workshop (IIRW) Integrated Reliability Workshop (IIRW), 2020 IEEE International. :1-4 Oct, 2020
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Photonics and Electrooptics
Reliability
Integrated circuit reliability
Reliability engineering
Layout
Fingers
Pattern matching
Debugging
Memory
NAND
DRAM
reliability verification
memory robustness
symmetry
matching
sense amplifier
topological pattern
electrical pattern
geometrical pattern
- Language
- ISSN
- 2374-8036
The demand for both non-volatile (NAND) and volatile dynamic random access memory (DRAM) chips in processor and application-specific integrated circuit (ASIC) designs has grown tremendously in recent years, due largely to rapid advances in semiconductor technology coupled with the trending popularity of low-power smart devices. This work demonstrates a proven automated reliability checking and debugging flow that combines electrical topologies with their geometrical patterns to ensure precise verification of reliability design rule compliance, especially for low-power high-speed applications using NAND/DRAM.