Suppressed boron penetration in P/sup +/-poly PMOSFETs with NO-nitrided SiO/sub 2/ gate dielectrics
- Resource Type
- Conference
- Authors
- Han, L.K.; Wristers, D.; Chen, T.S.; Lin, C.; Chen, K.; Fulford, J.; Kwong, D.L.
- Source
- 1995 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers VLSI technology, systems and applications VLSI Technology, Systems, and Applications, 1995. Proceedings of Technical Papers. 1995 International Symposium on. :36-39 1995
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Computing and Processing
Signal Processing and Analysis
Boron
MOSFET circuits
Annealing
CMOS technology
MOS capacitors
Capacitance-voltage characteristics
Dielectric devices
Electric variables
Degradation
Thickness control
- Language
- ISSN
- 1524-766X
Ultrathin NO-nitrided SiO/sub 2/ has been demonstrated to be a promising gate dielectric for dual-gate CMOS to alleviate the boron penetration problem in BF/sub 2/-implanted polysilicon gated p-MOSFETs. Results indicate that for both n/sup +/-poly n-MOSFETs and p/sup +/-poly p-MOSFETs, devices with NO-nitrided SiO/sub 2/ gate dielectrics exhibit superior electrical characteristics as well as device reliability as compared to those with control SiO/sub 2/.