Advanced Method for Defect Characterization Using Fail Bit Analysis and Critical Area Simulation
- Resource Type
- Periodical
- Authors
- Matsumoto, C.; Hamamura, Y.; Chida, T.; Tsunoda, Y.; Go, N.; Uozaki, H.; Miyazaki, I.; Kamohara, S.; Kaneko, Y.; Kanamitsu, K.
- Source
- IEEE Transactions on Semiconductor Manufacturing IEEE Trans. Semicond. Manufact. Semiconductor Manufacturing, IEEE Transactions on. 24(2):151-157 May, 2011
- Subject
- Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Estimation
Manufacturing
Accuracy
Semiconductor device modeling
Systematics
Integrated circuit modeling
Layout
Critical area analysis
fail bit map
integrated circuit layout
random defects
- Language
- ISSN
- 0894-6507
1558-2345
We propose an advanced approach to accurately estimate wafer-wafer variation of random defect density in each process layer $(D0_{l})$ using fail bit analysis and critical area simulation. The proposed method formulates $D0_{l}$ estimation using a linear programming model with constraint set of $D0_{l}$ is positive. The $D0_{{l}}$ estimation results are consistent with the test vehicles. We also illustrate some effective application results for yield improvement activities in the semiconductor manufacturing line.