Learning hardware using multiple-valued logic - Part 2: Cube calculus and architecture
- Resource Type
- Periodical
- Authors
- Perkowski, M.; Foote, D.; Qihong Chen; Al-Rabadi, A.; Jozwiak, L.
- Source
- IEEE Micro Micro, IEEE. 22(3):52-61 Jun, 2002
- Subject
- Computing and Processing
Hardware
Logic
Calculus
Hamming distance
Encoding
Set theory
Arithmetic
- Language
- ISSN
- 0272-1732
1937-4143
For Part 1 see ibid. vol.22, no.3 (2002). A massively parallel reconfigurable processor speeds up the logic operators performed in the learning hardware. The approach uses combinatorial synthesis methods developed within the framework of the logic synthesis approach in digital-circuit-design automation.