Learning hardware using multiple-valued logic - Part 1: introduction and approach
- Resource Type
- Periodical
- Authors
- Perkowski, M.; Foote, D.; Qihong Chen; Al-Rabadi, A.; Jozwiak, L.
- Source
- IEEE Micro Micro, IEEE. 22(3):41-51 Jun, 2002
- Subject
- Computing and Processing
Hardware
Reconfigurable logic
Field programmable gate arrays
Evolutionary computation
Computer networks
Machine learning
Genetic algorithms
Humans
Biological cells
Genetic mutations
- Language
- ISSN
- 0272-1732
1937-4143
The authors propose a learning-hardware approach as a generalization of evolvable hardware. A massively parallel, reconfigurable processor speeds up logic operators performed in learning hardware. The approach uses combinatorial synthesis methods developed within the framework of the logic synthesis in digital-circuit-design automation.