A 0.0046 mm2 low-distortion CMOS neural preamplifier for large-scale neuroelectronic interfaces
- Resource Type
- Conference
- Authors
- Trzpil-Jurgielewicz, Beata; Dabrowski, Wladyslaw; Hottowy, Pawel
- Source
- 2019 9th International IEEE/EMBS Conference on Neural Engineering (NER) Neural Engineering (NER), 2019 9th International IEEE/EMBS Conference on. :698-701 Mar, 2019
- Subject
- Aerospace
Bioengineering
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Engineered Materials, Dielectrics and Plasmas
Engineering Profession
Fields, Waves and Electromagnetics
General Topics for Engineers
Geoscience
Nuclear Engineering
Photonics and Electrooptics
Power, Energy and Industry Applications
Robotics and Control Systems
Signal Processing and Analysis
Transportation
Preamplifiers
Resistors
Transistors
Cutoff frequency
Logic gates
Nonlinear distortion
- Language
- ISSN
- 1948-3554
We present a design and analysis of nonlinear distortions for low-area integrated neural preamplifier with pseudoresistor-based AC coupling. We evaluate the distortions as a function of frequency, signal amplitude and sizing of the pseudoresistors. We describe a preamplifier design in 0.18 µm SOI CMOS technology with Total Harmonic Distortions (THD) below 1% in the full range of frequencies and amplitudes of extracellular neural signals. The circuit noise is 5.82 µV rms in the Local Field Potential (LFP) frequency range (1-300 Hz) and 4.45 µV rms in the action potential (AP) range (300 Hz-5 kHz). The preamplifier occupies silicon area of 0.0046 mm 2 and is suitable for recording systems with >10,000 channels per cm 2 of the chip area, providing high-fidelity amplification for large-scale neural interfaces.