Characterization of an Associative Memory Chip in 28 nm CMOS Technology
- Resource Type
- Conference
- Authors
- Annovi, Alberto; Calderini, Giovanni; Capra, Stefano; Checcucci, Bruno; Crescioli, Francesco; De Canio, Francesco; Fedi, Giacomo; Frontini, Luca; Garci, Maroua; Gentsos, Christos; Kubota, Takashi; Liberali, Valentino; Palla, Fabrizio; Shojaii, Jafar; Sotiropoulou, Calliope-Louisa; Stabile, Alberto; Traversi, Gianluca; Viret, Sebastien
- Source
- 2018 IEEE International Symposium on Circuits and Systems (ISCAS) Circuits and Systems (ISCAS), 2018 IEEE International Symposium on. :1-5 May, 2018
- Subject
- Components, Circuits, Devices and Systems
Power, Energy and Industry Applications
Signal Processing and Analysis
Cams
Clocks
Field programmable gate arrays
Power demand
Current measurement
Connectors
Associative memory
- Language
- ISSN
- 2379-447X
This paper presents the characterization of the new Associative Memory chip (version 7) designed and fabricated in 28 nm CMOS. The design aims at: enhancing links from/to FPGAs; increasing bandwidth thanks to full custom LVDS transceivers; and reducing power consumption and silicon area by means of new memory cells designed with full-custom approach. The design was submitted in December 2016; the prototypes were fabricated and packaged in a 17 × 17 Ball Grid Array (BGA) standalone package. Prototype characterization confirms the chip functionality. The final chip will be assembled in a System In Package (SiP) together with a bare FPGA die.